A prior art data processing system, for example a computer system, typically includes a number of components, each operating under an independent clock. When this occurs, each of the components of the data processing system typically transfers data at its own data transfer rate which is based on the clock of the respective component. Therefore, when data transfer is required between two components of different data transfer rates of the data processing system, a FIFO buffer is typically used that receives the data from a transmitting component at the data transfer rate of the transmitting component and sends the data to the receiving component at the data transfer rate of the receiving component.
When, however, the FIFO buffer does not contain any data to be transferred to the receiving component (i.e., empty), the receiving component is required to immediately stop reading data from the FIFO buffer in order to prevent invalid data to be transferred from the FIFO buffer to the receiving component. One prior art arrangement for stopping the data transfer when the FIFO buffer is empty is to reduce the data transfer rate between the FIFO buffer and the receiving component such that the empty condition in the FIFO buffer can be detected between any two data fetch cycles. Another prior art arrangement is illustrated in FIG. 1 which is described below.
Referring to FIG. 1, a data transfer system 10 is shown which includes a FIFO buffer 11 and a register circuit 13. FIFO buffer 11 is used to transfer data to register circuit 13 via bus 14. Register circuit 13 receives data from FIFO buffer 11 at a data transfer rate of register circuit 13. Register circuit 13 sends a request signal REQ to FIFO buffer 11 to control the data transfer from FIFO buffer 11 to register circuit 13. The REQ signal initiates each data fetch cycle.
FIFO buffer 11 also includes a counter 15. Counter 15 is used to generate a CONTROL signal. Counter 15 counts the number of data words or packets remaining in FIFO buffer 11. When counter 15 counts to zero, counter 15 asserts the CONTROL signal.
The CONTROL signal is applied to a breaking circuit 12. Breaking circuit 12 is also connected to register circuit 13 for receiving the REQ signal. Breaking circuit 12 generates an acknowledge signal ACK to FIFO buffer 11 and register circuit 13 in response to the REQ signal. Breaking circuit 12 asserts the ACK signal every time the REQ signal is asserted when the CONTROL signal is not asserted. Whenever the ACK signal is asserted, FIFO buffer 11 starts a data transfer cycle to transfer a data word or packet to register circuit 13. When, however, the CONTROL signal is asserted, breaking circuit 12 maintains the ACK signal deasserted regardless of the REQ signal. As described above, counter 15 asserts the CONTROL signal when counter 15 counts down to zero. This indicates that FIFO buffer 11 no longer holds any valid data to be transferred to register circuit 13. By causing breaking circuit 12 not to acknowledge the REQ signal, the data transfer between FIFO buffer 11 and register circuit 13 is effectively terminated.
Disadvantages are, however, associated with this prior art arrangement. One disadvantage is that in order to ensure that register circuit 13 is stopped in time to account for the worst case signal propagation of FIFO buffer 11, register circuit 13 cannot operate faster than FIFO buffer 11. This typically affects the data transfer rate between the two elements, which in turn affects the system performance of data transfer system 10.
In order to maximize the data transfer rate between FIFO buffer 11 and register circuit 13, one prior art solution is to allow counter 15 to assert the CONTROL signal when FIFO buffer 11 is almost empty. By doing so, register circuit 13 can transfer data at maximized transfer rate while still being able to stop the data transfer in time. One of the disadvantages of this prior art solution is that other arrangements are typically required to recover the remaining data from FIFO buffer 11 when the data transfer is stopped. Another disadvantage is that it is typically difficult to determine the appropriate threshold level at which counter 15 asserts the CONTROL signal to indicate FIFO buffer 11 is almost empty. If the threshold level is set at a relatively low level, register circuit 13 may not stop in time. If the threshold level is set at a relatively high level, FIFO buffer 11 may hold too much data when the data transfer is stopped.